A framework for multilevel interconnection technology

The process steps in general VLSI technology are examined, and categorized according to their contribution in the generation or elimination of surface topography. It is found that only a few combinations of processes lead to truly planarized processes. The metallization step is studied in detail. Process compatibility considerations eliminate the majority of possible ways to construct a metal layer, and leave only seventeen candidates for further consideration. Four out of the seventeen processes require no planarization and are considered promising as the base process for future interconnection technology. A common requirement of the four processes is the use of additive patterning instead of metal etching. Two examples of additive patterning are examined experimentally: one uses lift-off and the other uses selective electroless deposition. The flat surfaces obtained in these examples demonstrate the potential for future interconnection technologies with an unlimited number of conductive layers.<>