A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]

Author

Pathak, B. ; Cabrera, A. ; Christensen, G. ; Darwish, A. ; Goldman, M. ; Haque, R. ; Jorgensen, J. ; Kajley, R. ; Ly, T. ; Marvin, F. ; Monasa, S. ; Nguyen, Q. ; Pierce, D. ; Sendrowski, A. ; Sharif, I. ; Shimoyoshi, H. ; Smidt, A. ; Sundaram, R. ; Taub,

Author_Institution

Intel Corp., Folsom, CA, USA

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

32

Lastpage

33

Abstract

A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns asynchronous page mode access and synchronous burst reads up to 100 MHz with zero wait state.

Keywords

CMOS memory circuits; flash memories; memory architecture; 0.18 micron; 1.8 V; 100 MHz; 64 Mbit; CMOS; asynchronous page mode access; flexible read while write flash memory; multi-partition architecture; synchronous burst reads; zero wait state; Counting circuits; Delay; Differential amplifiers; Flash memory; Flexible printed circuits; Latches; Logic; Pulse amplifiers; Pulse circuits; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912420

Filename

912420