Performance of self-routing ATM switch under nonuniform traffic pattern

An asynchronous transfer model (ATM) switch which has lower hardware complexity than that of the output queuing switch is presented. The reduction in the hardware complexity is obtained without either losing the self-routing property or suffering from performance degradation under nonuniform traffic patterns. The switch consists of shift networks that are interconnected with distributors in two stages. Introducing the distributor between the stages of shift networks allows of packets to be distributed evenly to all the input ports of shift networks in the following stage. Although the switch becomes blocking, it retains the self-routing property and achieves the maximum throughput of 100% with only a small additional delay