Simplifying Boolean constraint solving for random simulation-vector generation

Author

Yuan, Jun ; Albin, Ken ; Aziz, Adnan ; Pixley, Carl

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

2002

fDate

10-14 Nov. 2002

Firstpage

123

Lastpage

127

Abstract

We present an algorithm for simplifying the solution of conjunctive Boolean constraints of state and input variables, in the context of constrained random vector generation using BDDs. The basis of our approach is the extraction of "hold-constraints" from the constraint system. Hold-constraints are deterministic and trivially resolvable; in addition, they can be used to simplify the original constraints as well as refine the conjunctive partition. Experiments demonstrate significant reduction in the time and space needed for constructing the conjunction BDDs, and the time spent in vector generation during simulation.

Keywords

Boolean functions; binary decision diagrams; circuit simulation; constraint handling; logic design; logic partitioning; logic simulation; binary decision diagrams; boolean constraint solution simplification; conjunction BDD; conjunctive partitioning; constrained random vector generation; deterministic/trivially resolvable hold-constraints; hold-constraint extraction; logic simulation; random simulation vector generation; state/input variable conjunctive Boolean constraints; Boolean functions; Clocks; Constraint optimization; Cost accounting; Data structures; Hardware; Input variables; Law; Legal factors; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

ISSN

1092-3152

Print_ISBN

0-7803-7607-2

Type

conf

DOI

10.1109/ICCAD.2002.1167523

Filename

1167523