Title :
Design and automatic generation of a CMOS NOR-NOR testable programmable logic array (CTPLA)
Author :
Pyo, Sam S. ; Yazdani, Mobashar
Author_Institution :
Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
Abstract :
A CMOS NOR-NOR testable PLA (CTPLA) which has a universal test set is discussed. Berkeley VLSI tools were used to implement and verify the design. The PLA contains an extra row and a column, along with a shift register and two cascades of exclusive-OR (EXOR) gates, to make it testable. The layout of the CTPLA was implemented such that the inherent regularity of the PLA can be maintained without undue compromise. A procedure which automatically generates the layout according to a given personalization was written. The test set detects all single stuck-at faults as well as crosspoint faults
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; integrated logic circuits; logic CAD; logic testing; Berkeley VLSI tools; CMOS NOR-NOR testable programmable logic array; CTPLA; PLA; automatic generation; stuck-at faults; Automatic logic units; Automatic testing; CMOS logic circuits; Circuit faults; Decoding; Fault detection; Logic design; Logic testing; Programmable logic arrays; Shift registers;
Conference_Titel :
Southeastcon '88., IEEE Conference Proceedings
Conference_Location :
Knoxville, TN
DOI :
10.1109/SECON.1988.194804
