A compiler-directed cache strategy for GaAs microprocessor architectures

Processor implementations in gallium arsenide (GaAs) technology have to contend with the problem of high-ratio off-chip to on-chip access times as compared to silicon technology. This problem can severely limit the throughput and remove the inherent advantages of GaAs implementations. This problem is addressed and a compiler-directed cache architecture is proposed to solve the problem. The architecture incorporates features to evaluate instruction streams both dynamically and statically for increased throughputs through RISC (reduced-instruction-set computer)-like features. Simulation results are also included to validate the proposal