Title :
An Energy Efficient Half-Static Clock-Gating D-Type Flip-Flop
Author :
Tam, Wing-Shan ; Wong, Oi-Ying ; Mok, Ka-Yan ; Kok, Chi-Wah ; Wong, Hei
Author_Institution :
City Univ. of Hong Kong, Kowloon
Abstract :
This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock- gating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 mum mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.
Keywords :
SPICE; flip-flops; logic design; SPICE simulation; clock-gating D-type flip-flop; dynamic master; half-static slave; mixed-signal CMOS technology; pass-transistor clock-gating circuitry; power dissipation; size 0.18 micron; CMOS technology; Clocks; Energy efficiency; Flip-flops; Master-slave; Parasitic capacitance; Power dissipation; Sequential circuits; Silicon; Switches;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0636-4
Electronic_ISBN :
978-1-4244-0637-1
DOI :
10.1109/EDSSC.2007.4450128
