Title :
Heavy ion testing and 3D simulations of Multiple Cell Upset in 65nm standard SRAMs
Author :
Giot, D. ; Roche, P. ; Gasiot, G. ; Autran, J.L. ; Harboe-Sorensen, R.
Author_Institution :
Central CAD & Design Solution group, Front-End Technol. & Manuf. Organ., Crolles, France
Abstract :
Heavy ions experiments are carried out on commercial 90 nm and 65 nm SRAMs. The contribution of single and multiple cell upsets are discussed as a function of the LET for different memory cell areas and for triple well usage. Once again, well engineering plays a key role on MCU and SEE response of SRAM. Full 3D TCAD simulations investigate the occurrence of parasitic bipolar effect.
Keywords :
SRAM chips; Full 3D TCAD simulations; heavy ion testing; multiple cell upset; parasitic bipolar effect; single cell upsets; size 65 nm; size 90 nm; standard SRAM; CMOS process; CMOS technology; Error correction codes; Manufacturing processes; Process design; Random access memory; SPICE; Silicon; Temperature sensors; Testing; 65nm; deep-Nwell; heavy ions; multiple-bit upset; multiple-cell upset; sensitive area; single-event upset; triple well;
Conference_Titel :
Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on
Conference_Location :
Deauville
Print_ISBN :
978-1-4244-1704-9
DOI :
10.1109/RADECS.2007.5205580
