DocumentCode :
2982667
Title :
FPGA — Based fast SSCH detector for 3G WCDMA systems using cyclic Hierarchical codes
Author :
Hussein, A. Abdulazeez ; Kadhim, A. Abdulkareem
Author_Institution :
Univ. of Technol., Baghdad, Iraq
fYear :
2011
fDate :
19-22 Feb. 2011
Firstpage :
533
Lastpage :
536
Abstract :
In 3G asynchronous WCDMA, the downlink receivers spent much time on acquisition and synchronization due to large computation time of the correlation and the detection of large codes (512) used. The work here deals with a reconfigurable FPGA design using VHDL hardware description language to provide realization of frame synchronization and code group identification to be complied with the 3GPP standard. The implementation is based on cyclic Hierarchical codes which show better cross correlation properties than that of CFRS (Comma Free Reed Solomon) codes. The proposed structure complexity is relatively low compared with that for CFRS: we need just one correlator instead of 16 and (32*16) ROM instead of (64*60) is required. A low complexity approximation is used to calculate the true magnitude of signals. Also different clock frequencies for correlation calculation are used. As a result, one slot is sufficient to obtain frame synchronization.
Keywords :
3G mobile communication; Reed-Solomon codes; broadband networks; code division multiple access; cyclic codes; field programmable gate arrays; hardware description languages; matched filters; 3G WCDMA system; CFRS code; FPGA; VHDL hardware description language; comma free Reed Solomon code; cyclic hierarchical code; downlink receiver; fast SSCH detector; Computer architecture; Correlation; Correlators; Microprocessors; Radiation detectors; Synchronization; FPGA; Matched Filter; WCDMA Cell search;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
GCC Conference and Exhibition (GCC), 2011 IEEE
Conference_Location :
Dubai
Print_ISBN :
978-1-61284-118-2
Type :
conf
DOI :
10.1109/IEEEGCC.2011.5752579
Filename :
5752579
Link To Document :
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