Comparison of power consumption among asynchronous design styles with their synchronous counterparts

Author

Kim, Seokjin ; Sridhar, Ramalingam

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

7

Abstract

This paper presents a power consumption comparison of synchronous and asynchronous standard cell implementations. The comparison is made with a simple data path block, a 4-bit serial parallel multiplier and the components used in the blocks. To provide a common basis of comparison, the standard cell design method is used with a suite of EDA tools for layout synthesis. Average power consumption is simulated using Spice3 with a power meter. The results of the simulation are tabulated and the advantages and disadvantages of each design are discussed

Keywords

SPICE; asynchronous circuits; cellular arrays; logic CAD; logic design; 4 bit; EDA tools; Spice3 simulation; asynchronous design; data path block; layout synthesis; low-power design; power consumption; power meter; serial parallel multiplier; standard cell; synchronous design; Asynchronous circuits; CMOS technology; Circuit testing; Computational modeling; Design methodology; Electronic design automation and methodology; Energy consumption; Logic design; Logic devices; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519178

Filename

519178