• DocumentCode
    298290
  • Title

    Low power selftimed design using CMOS differential circuits

  • Author

    Lu, Shih-Lien

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
  • Volume
    1
  • fYear
    1994
  • fDate
    3-5 Aug 1994
  • Firstpage
    15
  • Abstract
    An implementation of the four-states data representation using a modified CMOS differential logic is presented. By using this four-states representation power consumption of a selftimed circuit may be reduced by as much as half of the usual three-states encoding scheme
  • Keywords
    CMOS logic circuits; VLSI; integrated circuit design; logic design; pipeline processing; CMOS differential circuits; differential logic; encoding scheme; four-states data representation; low power selftimed design; power consumption; CMOS logic circuits; Capacitors; Clocks; Encoding; Energy consumption; Inverters; Parasitic capacitance; Pulsed power supplies; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
  • Conference_Location
    Lafayette, LA
  • Print_ISBN
    0-7803-2428-5
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1994.519180
  • Filename
    519180
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=298290