Design of tapered serial chains for reduced delay and power dissipation

Author

Cherkauer, Brian S. ; Friedman, Eby G.

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

29

Abstract

In this paper, the design issues relating to channel width tapered serially connected MOSFET chains are discussed. Channel width tapering is a method which is used to reduce the delay, area, and power dissipation of serial MOSFET chains. A design system for determining when tapering is appropriate, selecting the amount of tapering, and synthesizing the physical layout is presented. Physical layout issues unique to tapering are discussed, and fabricated test structures are described

Keywords

CMOS logic circuits; MOSFET; circuit layout CAD; combinational circuits; delays; integrated circuit design; logic CAD; CMOS; channel width tapered; combinatorial networks; delay; design system; physical layout; power dissipation; serially connected MOSFET chains; tapered serial chains; test structures; CMOS integrated circuits; CMOS logic circuits; Capacitance; Circuit testing; Integrated circuit synthesis; MOSFET circuits; Power MOSFET; Power dissipation; Propagation delay; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519183

Filename

519183