Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic

In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 4-input LUT-based structure of FPGAs. Furthermore, we have introduced a modification in the accumulator stage to achieve further savings. The proposed filter has been designed and synthesized with Altera Quartus II, and implemented on a Stratix FPGA device. Our results show reduced area requirements in comparison to previous LUT-less DA architectures