Formal description of data conversion algorithms for automatic synthesis

Author

Horta, N.C. ; Franca, J.E.

Author_Institution

Dept. de Engenharia Electrotecnica e de Comput., Inst. Superior Tecnico, Lisbon, Portugal

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

370

Abstract

This paper discusses the formal description of data conversion algorithms using a functional description language for automatic synthesis. The translation into an SFG representation is performed in order to identify the analog and digital partitions and then recognize possible circuit structures to implement the algorithm. The achieved representation allows an extension of the automatic synthesis of data conversion systems to a higher abstraction level and can lead to a generalized synthesis environment for data conversion systems

Keywords

VLSI; formal specification; functional languages; hardware description languages; mixed analogue-digital integrated circuits; signal flow graphs; CAD; SFG representation; VLSI; abstraction level; automatic synthesis; circuit structures; data conversion algorithms; formal description; functional description language; generalized synthesis environment; mixed analogue-digital ICs; signal flow graphs; Analog-digital conversion; Circuit synthesis; Data conversion; Design automation; Digital-analog conversion; Error correction; Partitioning algorithms; System testing; Topology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519259

Filename

519259