A 200 nV offset 6.5 nV//spl radic/Hz noise PSD 5.6 kHz chopper instrumentation amplifier in 1 /spl mu/m digital CMOS

Author

Qiuting Huang ; Menolfi, C.

Author_Institution

Integrated Syst. Lab., ETH Zurich, Switzerland

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

362

Lastpage

363

Abstract

The simplest and most effective way of minimizing the influence of charge injection, is illustrated. Unlike in sampled data circuits, where charge injection is inseparable from the sampling instant, in a chopper amplifier, a tiny time gap can be provided for the error charge pulses created by the input switches to die away before the signal is allowed to proceed to the output stage. Staggering the clock edges of the demodulator slightly behind those of the modulator provides such a guard time. A fully-integrated CMOS chopper amplifier in a single-poly, 1/spl mu/m CMOS technology, demonstrates the potential of the chopper scheme described.

Keywords

CMOS analogue integrated circuits; choppers (circuits); demodulators; instrumentation amplifiers; 1 micron; 200 nV; 5.6 kHz; CMOS technology; chopper instrumentation amplifier; clock edges; demodulator; digital CMOS; error charge pulses; guard time; time gap; CMOS technology; Choppers; Circuit noise; Clocks; Pulse amplifiers; Pulse circuits; Sampled data circuits; Sampling methods; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912674

Filename

912674