A 0.25 /spl mu/m CMOS 17 GHz VCO

In recent years, the design of CMOS RF oscillators at ever-higher frequencies has gained interest. The driving force for this evolution is the wireless market that evolves towards standards implementing higher bandwidths at higher frequency bands. This paper demonstrates that electronic systems adhering to future portable wireless as well as fixed-point wireless communication standards come within the grasp of standard CMOS technology. For this design, full optimization of all VCO building blocks is necessary, because in this design the inductor is no longer the sole and dominant source of phase noise and power loss. The optimized LC-tank and gain cell for the VCO-topology is obtained using an in-house design tool. The on-chip inductor utilizes all 4 available metal layers. The voltage-variable capacitance is realized by a varactor diode. In the global optimization, all contributions to phase noise and power loss of inductor, gain cell and diode cell are taken into account. Special attention is given to a high layout-symmetry in both floorplan and building blocks, to avoid the introduction of any additional asymmetry in the oscillation waveform. This design is in a standard CMOS 0.25 μm technology with 4 Al metal layers and 15 Ωcm substrate. The oscillator operates from 16.25 GHz to 17.715 GHz, when the control voltage is swept from 0.64 V to 1.4 V. This corresponds to a tuning range of 8.6% with a 16.98 GHz center frequency.