Title :
Validation of scheduling techniques to reduce peak temperature on an architectural level platform set-up
Author :
Chaturvedi, Vivek ; Thanarungroj, Pollawat ; Liu, Chen ; Quan, Gang
Author_Institution :
Dept. of Electr. & Comput. Eng., Florida Int. Univ., Miami, FL, USA
Abstract :
In this paper, we have proposed a novel architectural level simulation platform set-up to study the temperature characteristics of a processor system, when applying different speed scheduling schemes to execute the desired workload. Our simulation platform set-up is very practical as it combines the most practical simulation models, and uses the industry-standardized benchmark SPEC CPU2000 as the input to the platform. On this novel platform set-up we have compared two speed scheduling techniques, namely m-oscillation and a traditional optimal dynamic energy reducing speed scheduling technique, and have shown that m-oscillation can be as effective as the traditional approach in reducing the peak temperature of the system.
Keywords :
power aware computing; processor scheduling; SPEC CPU2000; architectural level simulation platform set-up; industry standardized benchmark; m-oscillation; optimal dynamic energy reducing speed scheduling technique; processor system; speed scheduling schemes; temperature characteristics; validation techniques; Benchmark testing; Integrated circuit modeling; Job shop scheduling; Processor scheduling; Real time systems; Schedules;
Conference_Titel :
Southeastcon, 2011 Proceedings of IEEE
Conference_Location :
Nashville, TN
Print_ISBN :
978-1-61284-739-9
DOI :
10.1109/SECON.2011.5752916