A Fast-Locked All-Digital Delay-locked Loop with non-50% Input Duty Cycle

A fast-locked all-digital delay-locked loop (DLL) with 50% output duty cycle is presented. A delay line using TSPC DFFs is re-used for the DLL and a time-to-digital converter. It results in a small-area and fast-locked DLL. The proposed DLL generates the output clock with 50% duty cycle in 4 cycles This DLL has been fabricated in a 0.18 um process. The core area is 350 um times105 um. The measured input frequency range is from 300 MHz to 500 MHz with input duty cycle of 40%~60%.