An architecture for integrated reliability simulators using analog hardware description languages

Author

GadelRab, S.M. ; Barby, J.A. ; Chamberlain, S.G.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

2

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

897

Abstract

A new architecture for integrated reliability simulators is presented. The architecture is compatible with analog hardware description language simulation environments. Simulator integration is achieved by incorporating the reliability evaluation routines into the component templates through the use of analog states. An internal simulation control mechanism is substituted for the external control shell found in conventional reliability simulators. The architecture supports iterative and multi-step reliability simulation schemes. A prototype reliability simulator for amorphous silicon circuits is also presented

Keywords

circuit reliability; digital simulation; hardware description languages; iterative methods; CAD tools; analog hardware description languages; component templates; integrated reliability simulators; internal simulation control mechanism; iterative simulation schemes; multi-step simulation schemes; simulation environments; Amorphous silicon; Circuit simulation; Computational modeling; Convergence; Degradation; Electronic mail; Hardware design languages; Integrated circuit reliability; Stress; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-2570-2

Type

conf

DOI

10.1109/ISCAS.1995.519909

Filename

519909