DocumentCode
298550
Title
Analysis of simultaneous switching noise
Author
Dolle, Michael
Author_Institution
Hyperstone Electron. GmbH, Konstanz, Germany
Volume
2
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
904
Abstract
With increasing system speed and I/O-count a noise phenomenon known as ΔI-Noise becomes more important and emerges as a limiting factor for reliable high speed chip-to-chip interconnections. Using a simplified model for CMOS drivers, the main effects of ΔI-Noise are investigated analytically and the impact of the model´s key parameters on the noise magnitudes and the driver delay is shown
Keywords
CMOS integrated circuits; delays; driver circuits; integrated circuit interconnections; integrated circuit noise; transient analysis; ΔI-noise; CMOS drivers; chip-to-chip interconnections; driver delay; limiting factor; noise magnitudes; simultaneous switching noise; Circuit noise; Delay effects; Differential equations; Driver circuits; Equivalent circuits; Integrated circuit interconnections; Power supplies; Semiconductor device modeling; Transient analysis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2570-2
Type
conf
DOI
10.1109/ISCAS.1995.519911
Filename
519911
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