A decimation filter architecture for GHz delta-sigma modulators

A means for implementing decimators for high-speed delta-sigma analog-to-digital converters is presented. The architecture exploits the single-bit nature of the output of the modulator and the symmetry present in the impulse response of a linear-phase FIR filter. Several hardware techniques, including table-lookup, pipelining and Wallace-tree adders, are needed to realize decimators capable of processing modulator data at GHz rates. A design example is given to demonstrate the hardware reduction possible with this architecture and to verify its speed