Title :
Exploration of area and performance optimized datapath design using realistic cost metrics
Author :
Choi, Kyumyung ; Levitan, Steven P.
Author_Institution :
Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
fDate :
30 Apr-3 May 1995
Abstract :
We present a novel technique for datapath allocation, which incorporates interconnection area and delay estimates based on dynamic floorplanning. In this approach, datapath area is minimized by minimizing the number of wires, routing tracks, and multiplexers, while performance is optimized by minimizing wire length. The simultaneous optimization of these physical cost metrics allows the system to explore realistic design solutions
Keywords :
circuit layout; circuit layout CAD; circuit optimisation; high level synthesis; area minimization; cost metrics; datapath allocation; delay; design; dynamic floorplanning; interconnection; multiplexers; performance optimization; routing tracks; wires; Clocks; Cost function; Delay effects; Delay estimation; Design optimization; High level synthesis; Multiplexing; Routing; Topology; Wires;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.519947