A high performance modular embedded ROM architecture

We describe a CMOS Read Only Memory architecture designed for high performances and low power consumption using domino logic. Short read delays are achieved using hierarchical evaluation of the read busses, at the price of some more material. Partial block evaluation allows power consumption to be greatly reduced for blocks with an important number of words, turning into an advantage this material increase. This architecture is well suited for memories embedded within synchronous systems due to it excellent speed/power performance. The architecture implementation is done as a parameterized generator, using a tiler and leaf cell approach. The leaf cells are designed using symbolic layout, providing a high degree of process independence. The tiler is written using the general purpose C language to ensure software portability