Title :
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS
Author :
Ashouei, Maryam ; Singh, Adit D. ; Chatterjee, Abhijit
Author_Institution :
Georgia Inst. of Technol., Atlanta
Abstract :
End-of-the-roadmap nanoscale CMOS is expected to suffer from significant defectivity due to manufacturing defects, random process variations, and wear-out during normal operational. To ensure acceptable yield and reliable operation of the circuit during its life-time, future circuits must be equipped with significant defect-tolerance capabilities. Traditional defect-tolerance approaches are too expensive to be applied to general purpose circuits. In this paper, we propose a defect-tolerant CMOS logic gate architecture that exploits the inherent functional redundancy in static CMOS. This is accomplished by reconfiguring the CMOS logic gate to a pseudo-NMOS-like gate in the presence of a defect. The resulting defect-tolerant logic architecture incurs only a modest area overhead. The proposed gate design can tolerate defects in either the pull-up or pull-down network of the gate. The architecture can tolerate multiple defects across the logic gates of a CMOS logic circuit. The effectiveness of the proposed defect tolerance technique and its impact on circuit delay and power is studied. It is shown that the technique imposes little delay overhead (less than 6%) but incurs power dissipation overhead (less than 20%) in the presence of defects.
Keywords :
CMOS logic circuits; integrated circuit reliability; nanoelectronics; redundancy; CMOS logic gate; defect tolerance; functional redundancy; nanoscale CMOS; pseudo N/PMOS; pull-down network; pull-up network; static CMOS; CMOS logic circuits; CMOS process; CMOS technology; Circuit faults; Circuit simulation; Delay; Logic gates; Reconfigurable logic; Redundancy; Very large scale integration;
Conference_Titel :
VLSI Design, 2008. VLSID 2008. 21st International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-7695-3083-4
DOI :
10.1109/VLSI.2008.104