DocumentCode :
2987505
Title :
PowerBit - power aware arithmetic bit-width optimization
Author :
Gaffar, Altaf Abdul ; Clarke, Jonathan A. ; Constantinides, George A.
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. London
fYear :
2006
fDate :
Dec. 2006
Firstpage :
289
Lastpage :
292
Abstract :
In this paper we present a novel method reducing the dynamic power consumption in FPGA-based arithmetic circuits by optimizing the bit-widths of the signals inside the circuit. The proposed method is implemented in the tool PowerBit, which makes use of macro models parameterized by word-level signal statistics to estimate the circuit power consumption during the optimization process. The power models used take in to account the generation and propagation of signal glitches through the circuit. The bit-width optimization uses a static analysis technique which is capable of providing guaranteed accuracy in the design outputs. We show that, for sample designs implemented on FPGAs that improvements of over 10% are possible for multiple bit-width allocated designs optimized for power compared to designs allocated uniform bit-widths
Keywords :
circuit optimisation; field programmable gate arrays; logic design; PowerBit; arithmetic circuits; field programmable gate arrays; power aware arithmetic bit-width optimization; signal glitches; word-level signal statistics; Arithmetic; Circuits; Design optimization; Energy consumption; Field programmable gate arrays; Optimization methods; Power generation; Signal generators; Signal processing; Statistics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on
Conference_Location :
Bangkok
Print_ISBN :
0-7803-9729-0
Electronic_ISBN :
0-7803-9729-0
Type :
conf
DOI :
10.1109/FPT.2006.270330
Filename :
4042452
Link To Document :
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