DocumentCode
298849
Title
Benchmarking MOS transistor models with respect to capacitances and charges for analog applications
Author
Feldmann, U. ; Rahm, A. ; Muira-Mattausch, M.
Author_Institution
Corp. Res. & Dev., Siemens AG, Munich, Germany
Volume
2
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
1352
Abstract
Tsividis and Suyama (1994) have given benchmark circuits to assess model quality for analog applications. They are mainly based on the drain current quality check. We propose here benchmark circuits with respect to capacitances and charges. The most serious failure of existing models is related to the charge partitioning to the source and the drain side. The influence of the failure on real applications will be demonstrated
Keywords
MOS analogue integrated circuits; MOSFET; SPICE; capacitance; circuit CAD; circuit analysis computing; integrated circuit design; semiconductor device models; semiconductor device reliability; MOS transistor models; benchmark circuits; capacitance; charge partitioning; device failure; drain current quality check; Analog circuits; Analytical models; Application software; Benchmark testing; Capacitance; Circuit analysis; Circuit testing; Design automation; MOSFETs; Varactors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2570-2
Type
conf
DOI
10.1109/ISCAS.1995.520397
Filename
520397
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