An asynchronous FIFO with fights: case study in speed optimization

This paper describes an experiment in optimizing digital integrated circuits to maximize operating speeds. The circuit in question is an asynchronous FIFO originally designed for ultra-high-speed. To obtain an even higher throughput, we consider optimizations and local changes of the circuits by using fights, relative delay constraints, and asymmetric and skewed gates. We propose a transistor sizing procedure applicable in these conditions. Part of our procedure is based on the principles of logical effort; in addition, we investigate how to size the circuit with fights. The resulting circuit implemented in TSMC´s 0.35 μm technology can yield throughputs over 1500 millions items per second