Single chip implementation of feature measurement for LPC-based speech recognition

A single chip implementation of LPC-based feature measurement has been developed using the AT&T Bell Laboratories Digital Signal Processor and has been verified by both numerical simulation and system use. The feature measurement circuit, called the FXDSP, performs eighth-order LPC analysis continuously in real time. It receives mu-law-encoded telephone bandwidth speech at a 6.667 kHz sampling rate from a standard CODEC and produces a feature vector consisting of the log energy, nine amplitude-normalized autocorrelation coefficients, and nine LPC-based test pattern coefficients for each analysis frame of speech. Feature vectors are output continuously at a frame period of 15 msec. The feature measurement program requires 1023 locations of the 1024 available in on-chip program ROM, 211 of 256 available RAM locations, and 75% of available real time. The output of the FXDSP has been compared to a floating point FORTRAN program calculating on identical speech waveforms. An LPC-based log likelihood distance between floating point simulation and FXDSP implementation was found to be negligibly small (average distance of 0.021) when compared with distances for word matches in speech recognition (average distance of 0.45).