DocumentCode
2989309
Title
On the P+ guard ring sizing strategy to shield against substrate noise
Author
Bronckers, S. ; Vandersteen, G. ; Van der Plas, G. ; Rolain, Y.
Author_Institution
IMEC, Leuven
fYear
2007
fDate
3-5 June 2007
Firstpage
753
Lastpage
756
Abstract
Substrate noise coupling remains a major problem for a system on a chip (SoC) design. Coupling between various parts of the system through the substrate may cause malfunctioning of the system. Guard rings are frequently used to shield the analog circuitry from the noisy digital circuits. In this paper measurements show that the isolation does not increase linearly with the guard ring width. These experimental results reveal that starting from a guard ring width above 16 mum, the isolation saturates with the guard ring width. It also shows that the effectiveness of the guard ring strongly depends on its ground connection. The effectiveness of the proposed guard rings against substrate noise is demonstrated on a 5-7 GHz LC voltage controlled oscillator (VCO), designed in a CMOS 130 nm technology.
Keywords
CMOS integrated circuits; MMIC oscillators; integrated circuit noise; voltage-controlled oscillators; CMOS; LC voltage controlled oscillator; P+ guard ring sizing strategy; SoC; VCO; frequency 5 GHz to 7 GHz; noisy digital circuits; size 130 nm; substrate noise; substrate noise coupling; system on a chip; CMOS technology; Circuit noise; Costs; Coupling circuits; Crosstalk; Digital circuits; Integrated circuit noise; Isolation technology; Radio frequency; Voltage-controlled oscillators; CMOS integrated circuit; Substrate noise; guard ring; isolation; voltage controlled oscillator;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE
Conference_Location
Honolulu, HI
ISSN
1529-2517
Print_ISBN
1-4244-0530-0
Electronic_ISBN
1529-2517
Type
conf
DOI
10.1109/RFIC.2007.380992
Filename
4266540
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