Image processing address generator chip

Accurate high speed rotation, warpage, translation, or rescaling of a two-dimensional image requires large RAMs, fast multiplier accumulators (MACs), and sophisticated address generators and controllers. TRW is designing a CM36 integrated circuit that generates the necessary control signals and data and coefficient addresses, economically replacing roughly 100 MSI and SSI components. The chip´s target speed of 10 MHz is well matched to commercially available memories and MACs. With its versatile instruction set, the chip efficiently supports all first and second order image transforms, plus two dimensional filtering with a kernel size of up to 225 pixels.