Delay constraints and admission control in ATM networks

The architecture of a typical ATM (asynchronous transfer mode) switch is reviewed, and the problem of handling both continuous bit-oriented and bursty traffic with low loss and delay requirements is considered. A buffer architecture that is capable of handling both delay sensitive and loss sensitive traffic is examined, and a scheme to allocate network resources, i.e. bandwidth and buffer space, to individual circuits to ensure acceptable delay and loss performance is presented. A set of admission control rules to accept connections with this buffer architecture is developed. The control rules presented are easy to implement and evaluate and lead to fair utilization of network resources in the presence of bursty traffic