Floorplanning with datapath optimization

This paper presents a floorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of functional units and the schedule. The tool has combined two novel approaches: 1-A placement and routing model to handle different architectural topologies (mux. and/or bus based) suitable for FPGA´s. 2-An efficient formulation for the binding of register/interconnect and combined floorplanning. The complexity of the architectural and floorplanning model, and of the cost function, have led us to the use of a stochastic optimization process. The running time of the whole process indicates the viability of the method. We show through various examples how the floorplanner improves the area and critical path delay of the datapath compared to a plain floorplanner. The improvement is about 20% for the critical path delay when this objective is a stringent constraint