A 550 MHz 9.3 mW CMOS frequency divider

Author

Wu, Jiin-Chuan ; Chang, Hun-Hsien

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

1

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

199

Abstract

This paper deals with the design of a high speed CMOS programmable frequency counter design. It is the heart of a frequency synthesizer IC. By using an end-of-count (EOC) detecting algorithm, and a modified ripple down counter, we designed a high performance 14-bits programmable counter. The programming values N can be from 3 to 16384. The chip is implemented in 0.8 μm CMOS technology, active area die size is 440 μm×510 μm. The counter was measured to operate at 550 MHz with 5V power supply voltage, 317 MHz with 3V power supply voltage, and 135 MHz with 2V power supply voltage. It can be used to design frequency synthesizer ICs for radio communication products

Keywords

CMOS logic circuits; counting circuits; frequency dividers; frequency synthesizers; 0.8 micron; 135 to 550 MHz; 2 to 5 V; 9.3 mW; CMOS frequency divider; active area die size; end-of-count detecting algorithm; frequency synthesizer IC; programmable frequency counter; programming values; radio communication products; ripple down counter; Algorithm design and analysis; CMOS technology; Counting circuits; Frequency conversion; Frequency synthesizers; Heart; Integrated circuit synthesis; Power measurement; Power supplies; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-2570-2

Type

conf

DOI

10.1109/ISCAS.1995.521485

Filename

521485