A new architecture for analog boundary scan

The IEEE Boundary Scan Standard 1149.1 has been widely used for digital circuit testing. A similar standard for analog circuits is yet to be set up. In this paper we propose a new analog boundary scan architecture which is similar to the IEEE Std. 1149.1. The basic analog boundary scan cell, the defined instructions, the associated operations, and the control circuitry are described. The advantages of this architecture include: (1) Signal at various test points can be sampled simultaneously, (2) test stimuli can be injected to various test points simultaneously, and (3) test stimuli loading and test response outputting can be done simultaneously