Design of Single-Stage Folded-Cascode Gain Boost Amplifier for 100mW 10-bit 50MS/s Pipelined Analog-to-Digital Converter

Author

Musa, Rohana ; Yusoff, Yuzman ; Yew, Tan Kong ; Ahmad, Mohd Rais

Author_Institution

AMS IC Design Group, Berhad

fYear

2006

fDate

Oct. 29 2006-Dec. 1 2006

Firstpage

800

Lastpage

804

Abstract

This paper presents the design and simulation of high speed, high gain and low power fully differential operational amplifier (op-amp) implemented in 0.35 um CMOS technology. The op-amp was designed for sample-and-hold stage of 100 mW 10-bit 50 MS/s pipelined analog-to-digital converter. A topology of single-stage folded-cascode with gain boosting technique is employed in this op-amp. The simulated op-amp achieves a DC gain of 95dB, unity gain bandwidth of 412 MHz and phase margin of 75 degrees. The settling time is 7.5 ns and the op-amp consumes power 12.8 mW with supply voltage of 3V.

Keywords

CMOS integrated circuits; analogue-digital conversion; operational amplifiers; CMOS technology; high gain fully differential operational amplifier; high speed fully differential operational amplifier; low power fully differential operational amplifier; pipelined analog-to-digital converter; power 100 mW; single-stage folded-cascode gain boost amplifier; size 0.35 mum; word length 10 bit; Analog-digital conversion; Boosting; CMOS technology; Differential amplifiers; Equations; Frequency; High power amplifiers; Operational amplifiers; Topology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

0-7803-9730-4

Electronic_ISBN

0-7803-9731-2

Type

conf

DOI

10.1109/SMELEC.2006.380747

Filename

4266730