Designing an asynchronous FPGA processor for low-power sensor networks

Battery-powered sensor nodes call for low power consumption. As a crucial component, a power-efficient sensor network processor greatly reduce the overall power consumption of a node. In the paper, we propose a low-power asynchronous event-driven sensor network processor mapped onto an off-the-shelf clocked FPGA. Since the processor employs a bundled-data asynchronous encoding scheme, we define a design flow that can use commercial synchronous design tools. No global clock is needed when the processor is in an idle state, thus the standby active power consumption is zero. The use of asynchronous design also results in a quick wakeup response with little design and power overheads. Moreover, an event-driven architecture is proposed to minimize the execution overheads caused by exceptions, interrupts and MMU handling of a conventional microprocessor.