Detection of temperature sensitive defects using ZTC

Author

Long, Ethan ; Daasch, W. Robert ; Madge, Robert ; Benware, Brady

Author_Institution

IC Design & Test Lab., Portland State Univ., OR, USA

fYear

2004

fDate

25-29 April 2004

Firstpage

185

Lastpage

190

Abstract

This work attempts to improve the common understanding of multiple temperature testing by presenting previously unpublished data as well as deriving a simple model for bounding an IC´s performance within the three dimensional space defined by VDD, frequency, and temperature. The model is used to design new temperature screens to improve the resolution between healthy and defective ICs. Temperature based test data is presented for Scan, LBIST, and TDF based MinVDD measurements as well as transistor characteristics needed to parameterize the model. The test vehicles used are 0.25 μm and 0.18 μm CMOS ASICs fabricated by LSI logic.

Keywords

CMOS integrated circuits; application specific integrated circuits; integrated circuit testing; large scale integration; 0.18 micron; 0.25 micron; CMOS ASIC test vehicles; LSI logic; MinVDD measurements; multiple temperature testing; temperature based test data; temperature sensitive defect detection; three dimensional space; transistor characteristics; zero temperature coefficient; Frequency; Integrated circuit modeling; Integrated circuit testing; Large scale integration; Logic design; Logic testing; Power supplies; Semiconductor device modeling; Temperature sensors; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2004. Proceedings. 22nd IEEE

ISSN

1093-0167

Print_ISBN

0-7695-2134-7

Type

conf

DOI

10.1109/VTEST.2004.1299242

Filename

1299242