Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers

Formal verification plays an important role in the verification of complex processors. In this paper, we discuss the usage and impact of equivalence checking in the verification of TI´s TMS320C27X DSP core. During various phases of the design, we need to ensure the correctness of the design, a significant part of which could be best done with an equivalence checker. (For example, verifying the functionality of the netlist after CTS insertion with the one before CTS insertion). The capabilities and limitations of the commercial equivalence checkers are studied and a set of guidelines for their effective usage during different phases of the design is proposed. Also, a set of RTL coding guidelines to make the design equivalence checker friendly is detailed. Further, we discuss constrained mode equivalence checking which could be used if the implementation design is a super set of a reference design. The verification cycle time reduction and the salient features of an automated methodology that was developed specifically for our DSP core are described