DocumentCode
2994182
Title
A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability
Author
Ohtake, Satoshi ; Nagai, Shintaro ; Wada, Hiroki ; Fujiwara, Hideo
Author_Institution
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
fYear
2001
fDate
2001
Firstpage
331
Lastpage
334
Abstract
This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing
Keywords
VLSI; design for testability; fault location; integrated circuit testing; logic testing; sequential circuits; DFT method; RTL circuits; at-speed testing; complete fault efficiency; data path; fault efficiency; fixed-control testability; hardware overhead; nonscan design-for-testability method; register-transfer level circuits; Automatic test pattern generation; Circuit faults; Circuit testing; Costs; Design for testability; Design methodology; Hardware; Information science; Logic testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-6633-6
Type
conf
DOI
10.1109/ASPDAC.2001.913328
Filename
913328
Link To Document