High-level design for asynchronous logic

Author

Smith, Ross ; Ligthart, Michiel

fYear

2001

fDate

2001

Firstpage

431

Lastpage

436

Abstract

Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete high level design flow for asynchronous circuits based on register transfer level (RTL) VHDL using commercial simulation and synthesis tools. Contrary to previous asynchronous approaches, the proposed RTL methodology closely resembles familiar synchronous design styles

Keywords

asynchronous circuits; hardware description languages; high level synthesis; logic simulation; asynchronous approaches; asynchronous logic; design flow; high-level design; register transfer level VHDL; self-timed logic; synchronous design styles; Asynchronous circuits; Circuit simulation; Circuit synthesis; Clocks; Design methodology; Electronics industry; Hardware design languages; Logic circuits; Logic design; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913346

Filename

913346

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2994557