LLA: A low-latency asynchronous control with applications

In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circuit has only two gate delays in its critical path, which is faster compared to other works reported in the literature. Two applications of the design are shown to demonstrate its efficiency. The first is a 16-bit FIFOs and the second is a 4times4 multipliers which are designed both using LLA and GasP approaches. The designs are then simulated using HSPICE and 0.18 mum CMOS technology parameters. The results show a latency improvement of about 38% in FIFOs and 18% in multipliers without any considerable degradation in other parameters such as power and throughput. The energy-delay curves also show better overall performance of LLA.