Title :
Long wires and asynchronous control
Author :
Ho, Ron ; Gainsley, Jon ; Drost, Robert
Author_Institution :
Sun Microsystems Res. Labs., Mountain View, CA, USA
Abstract :
As integrated circuit technologies get smaller, circuit and architectural trends make transmitting data across long on-chip wires increasingly important yet increasingly expensive in both latency and throughput. Inserting repeaters can reduce latency by breaking up long wires with gain stages but offers only limited throughput improvement, while breaking long wires with clocked latches improves latency and throughput but requires generating fast local clocks. In contrast, asynchronous handshaking over long wires can improve both latency and bandwidth with lower control overhead. We introduce simple latency models that relate best stage separation to technology parameters. In addition, the transactional nature of handshaking presents a fundamental limitation on throughput exacerbated by long wires. We present twin request/acknowledge control scheme that overcomes this throughput cost.
Keywords :
asynchronous circuits; clocks; integrated circuit interconnections; architectural trends; asynchronous control; asynchronous handshaking; clocked latches; control overhead; gain stages; integrated circuit technologies; latency models; latency reduction; local clocks; long on-chip wires; stage separation; technology parameters; throughput cost; throughput improvement; twin request-acknowledge control scheme; Asynchronous circuits; Clocks; Costs; Degradation; Delay; Integrated circuit technology; Latches; Repeaters; Throughput; Wires;
Conference_Titel :
Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on
Print_ISBN :
0-7695-2133-9
DOI :
10.1109/ASYNC.2004.1299307