Title :
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times
Author :
Hosokawa, Toshinon ; Yoshimura, Masayoshi ; Ohta, Mitsuyasu
Author_Institution :
Corp. Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Tokyo, Japan
Abstract :
As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As a result, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method
Keywords :
boundary scan testing; design for testability; flip-flops; integrated circuit testing; large scale integration; logic testing; sequential circuits; DFT strategies; LSI; design for testability strategies; flip-flops; full/partial scan designs; scan path; test application time; test application times; test point insertions; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Design for testability; Design methodology; Flip-flops; Large scale integration; Pins; Semiconductor device testing;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913355
