Acceleration techniques for dynamic vector compaction

We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly improve the computation times without adversely affecting the quality of test sets that can be derived using state-of-the-art compaction methods. Our techniques are based on three key ideas: (1) identification of support sets, (2) target fault switching, and (3) use of dynamic equivalent and untestable fault analysis, All these techniques are useful in significantly reducing the number of faults that have to be considered by a test generator or a fault simulator in a dynamic vector compaction system. For fault simulation, support sets quickly identify a large subset of faults that are guaranteed to be undetectable by a given input sequence. For test generation, support sets identify a large subset of faults that are guaranteed to be undetectable by any extension of a partially specified test sequence. Experimental results on ISCAS 89 benchmark circuits and large production VLSI circuits are included. For full scan designs, our acceleration techniques reduce the overall computation times by a factor of 2 to 3 without adversely affecting the quality (size) of the computed test sets or their fault coverages. The improvement factors obtained are higher for larger circuits. The acceleration techniques enabled the computation of compact test sets for large production circuits that the base test generation system was unable to process in more than 2 CPU days on a Silicon Graphics MIPS 4400 workstation. Results for sequential circuits also show that our acceleration techniques significantly improve the computation times for dynamic vector compaction.