DocumentCode
2995071
Title
Fault tolerant distributed routing algorithms for mesh Networks-on-Chip
Author
Lehtonen, Tapio ; Liljeberg, Pasi ; Plosila, Juha
Author_Institution
Turku Centre for Comput. Sci. (TUCS), Turku, Finland
fYear
2009
fDate
9-10 July 2009
Firstpage
1
Lastpage
4
Abstract
The reliability of networks-on-chip can be increased by developing routing algorithms that provide fault tolerance. Distributed routing algorithms are a class of algorithms where the routing decisions are made without knowledge of the global state of the network. The paper presents a distributed routing algorithm, which targets to maximal fault tolerance. Total of 11 different algorithms are analyzed in their fault tolerance and average hop count using a dedicated in-house C++ simulator. Five of the algorithms are variations of the proposed algorithm and the rest are references or algorithms presented in literature. The developed fully adaptive algorithm is shown to provide superior fault tolerance. The best deadlock-free algorithm is the variation based on the north-last turn model. In the class of minimal algorithms the dynamic xy algorithm provides the highest fault tolerance.
Keywords
C++ language; electronic engineering computing; fault tolerance; logic design; network routing; network-on-chip; C++ simulator; deadlock-free algorithm; distributed routing algorithm; fault tolerance; mesh network-on-chip; Algorithm design and analysis; Distributed control; Error correction; Fault tolerance; Heuristic algorithms; Network topology; Network-on-a-chip; Protection; Routing; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Circuits and Systems, 2009. ISSCS 2009. International Symposium on
Conference_Location
Iasi
Print_ISBN
978-1-4244-3785-6
Electronic_ISBN
978-1-4244-3786-3
Type
conf
DOI
10.1109/ISSCS.2009.5206180
Filename
5206180
Link To Document