Pipelined Delta Sigma Modulator Analog to Digital Converter

A two stage Pipelined Delta Sigma Modulator ADC is presented for broad band, high resolution applications. The unique architecture incorporates a first order delta sigma modulator in each stage and combines the most significant bits of the first stage with the second stage output to produce 11-13 bit resolution. The input bandwidth is 62.5 MHz and the sampling frequency of 1 GHz results in an over sampling ratio of 8 for the first order modulators. MATLAB simulations for the two stage ADC show 13-15 bit resolution. A transistor level design in 0.18 um CMOS for the two stage ADC was captured and simulated with Cadence show 12 bit resolution with a 50 MHz input. The ADC was fabricated in 0.18 um CMOS technology on a 10 square millimeter die.