Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB(R)

Author

Haldar, Malay ; Nayak, Anshuman ; Choudhary, Alok ; Banerjee, Prith

Author_Institution

MACH Design Syst. Inc., Schaumberg, IL, USA

fYear

2001

fDate

2001

Firstpage

645

Lastpage

648

Abstract

We present a compiler that takes high level algorithms described in MATLAB and generates an optimized hardware for an FPGA with external memory. A framework is described to detect and exploit opportunities to pipeline loops in an optimal way. Effectiveness of the framework is demonstrated by synthesizing some image and signal processing applications. Starting from the MATLAB description of the applications, hardware is synthesized that runs on a Xilinx XC4028. The synthesized designs are equivalent to manually optimized designs in performance

Keywords

field programmable gate arrays; high level synthesis; image processing; logic CAD; pipeline processing; signal processing; FPGA; MATLAB; Xilinx XC4028; automated synthesis; compiler; external memory; hardware optimization; high level algorithm; image processing; pipelined design; signal processing; Algorithm design and analysis; Field programmable gate arrays; Finite impulse response filter; Hardware; Image processing; MATLAB; Pipeline processing; Signal design; Signal processing; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913382

Filename

913382