Reliability impacts of multiple-bit-per-chip RAMs

Author

Jacobson, David W.

Author_Institution

IBM Corp., Rochester, NY, USA

fYear

1988

fDate

26-28 Jan 1988

Firstpage

302

Lastpage

305

Abstract

The author considers the need to use error-correcting codes which have the same efficiency of the traditional single-bit-error-correcting and double-bit-error-detecting (SBEC-DBED) codes but which can be used with the current multiple-bit-per-chip organizations. A short summary is presented of memory chip and memory card configurations along with common chip failure modes and how SBEC-DBED and DBEC-TBED (double-bit-error-correcting-triple-bit-error-detecting) error-correcting codes are used to overcome these failures. This is followed by a description of the problem with the use of multiple-bit-per-chip organizations. Solutions that would satisfy the reliability requirements are included

Keywords

error correction codes; failure analysis; integrated memory circuits; random-access storage; reliability; common chip failure modes; double-bit-error-detecting codes; error-correcting codes; memory card configurations; memory chip; multiple-bit-per-chip RAM; reliability requirements; triple-bit-error-detecting codes; Computer errors; Costs; Decoding; Error correction codes; Jacobian matrices; Logic; Maintenance; Random access memory; Read-write memory; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability and Maintainability Symposium, 1988. Proceedings., Annual

Conference_Location

Los Angeles, CA

Type

conf

DOI

10.1109/ARMS.1988.196465

Filename

196465