OFF stage leakage analysis from Power Gating application in deep sub-micron technology

It is ubiquitous that high performance integrated circuits designs are commonly suffers from total chip power consumption. Moreover, when we are marching towards deeper sub-micron technology from process scaling, the transistor leakage it self had became more and more dominant to the total component power which is unavoidable. Clever employment of power gating / sleep transistor / MTCMOS technology can help to shut off leakage power from un-use blocks. However at high temperature and fast skew, OFF stage leakage current will still be very significant if wrong implementation strategy was employed. This paper described the circuit analysis, optimization strategies and design methodology to tackle this issue head on. Details break down on the circuit modeling and design trade off on Power Gating FETs was described in this paper including simulation results and equations to aid the illustrations. The OFF stage power saving using MTCMOS was re-evaluated for total leakage minimization.