A Resource-Efficient Decoder Architecture for LDPC Codes

A novel architecture for the LDPC decoder with Chinese DTTB standard is presented in this paper. Two kinds of schemes to do the minimizing operations in the horizontal process of min-sum algorithm are compared, and then a foldable horizontal process unit is developed to support the splitting-matrix architecture, which is a reuse architecture based on check matrix splitting to increase the resource efficiency of the decoder. Theoretical analyses and implementation results are both provided to demonstrate that the decoder using this architecture has higher resource utilization efficiency than classical decoder. In addition, the new architecture can also be applied to other LDPC decoder, especially to LDPC codes with long code words.